When designing circuitry using dynamic logic such as domino logic gates, it is often the case that signals produced by these domino gates are dual-rail, with one clocked signal representing a data 1 and the other clocked signal representing a data 0. These signals are in the appropriate form to apply as inputs to a subsequent dynamic gate, such as a domino logic gate. In these systems, some of the slower circuitry may be implemented in static logic in order to reduce power dissipation. However, dual rail clocked signals are not in the form that the static logic portion of the circuitry can generally use. In order to be useful to static gates, it is customary that the signals be latched.
FIG. 1 shows typical clocked signal and latched signal waveforms. Whereas clocked signals rise on the rising edge of a clock signal elk after some delay and fall on its falling edge with some delay, latched signals transition in either direction (both transition directions shown in FIG. 1) on the rising edges of elk after some time delay.
One application where it may be desirable to convert clocked signals to static signals is where the signal must simply be sent through one or more levels of latch in order to pass it through one or more stages of a pipeline. Normally this can be considered to occur in two steps. In a first step a circuit converts the clocked signals to static signals, then in a second step the static signals are clocked by the first level of latch. One circuit which can combine these two operations is a clocked RS latch. When circuits operate at very high frequencies, pipelining signals through registers becomes increasingly difficult, because the delays of the latches and registers themselves become a large fraction of the clock cycle, leaving little additional delay for other operations, which might include simple logic functions. In that case, combining the functions of dynamic to static conversion and latching results in a substantial reduction in latency, which can be a requirement at high frequencies for certain applications.
FIG. 2A shows a schematic of a conventional and-or-invert (AOI) based clocked RS latch circuit 200. RS latch circuit 200 comprises a pair of cross coupled AOI21 gates 201 and 202 and output inverters 206 and 207. FIG. 2B shows a schematic of a conventional AOI21 gate 200 that can implement AOI21 gates 201 and 202. Referring again to FIG. 2A, the inputs to RS latch circuit 200 are two dual rail clocked signals (D, Dx) and its outputs are complementary static latched signals (L, Lx). It is expected that D and DX are not both high at the same time. When the CLK and D inputs are both high, the AOI gate latch node NX goes low and the latch output L goes high. NX going low forces its other latch node N high given that DX is low, and LX goes low. It is intended that when the CLK is high, both D and DX are not allowed to be high; at least one of them must be low. There are two signal inversions from D rising to L rising, and three signal inversions to LX falling. Two of the inversions are through complex gates. Moreover, there are six (6) transistors pulling up or down on latch nodes Nx and N. As shown in FIG. 2B, 4 transistors are shown directly coupled to node Y which becomes the latch node in RS latch circuit 200, with 2 additional transistor directly coupled to node Y via the cross coupling connection back to the input of the other AIO21 gate. As a result, the delay of AOI-based RS latch circuit 200 is relatively long.
In spite of its latency issues, clocked RS latch circuit 200 has advantages over using a standard clocked D-type latch, an example of which is clocked D-type latch 300 shown in FIG. 3. For D-type latch 300, if the data (D) input, which is assumed to be a clocked signal like the D input in FIG. 2A, does not align its edges precisely with the clock, problems generally occur. If the leading edge of the data is late, the latch 300 may start flipping towards the wrong state, only to have to recover later from this false transition. If the trailing edge of the data is early, the clock will then start to capture an incorrect final value. For that reason, the AOI-based RS latch 200 shown in FIG. 2A may be preferable compared to D-type latch 300, although its latency may not be as good as desired. What is needed is a robust clocked latch design that provides less latency.